This invention relates to CMOS fabrication on ultra-thin silicon-on-insulator (SOI), and specifically to a method and structure for preserving an ultra-thin silicon layer during fabrication.
When the thickness of a top silicon layer approaches 20 nm, a gate sidewall etching process produces a high density of voids in the silicon in the source/drain regions. This high density of voids degrades the performance of the device and production yield. This problem becomes more severe as the top silicon thickness is reduced, which is required in shorter channel length device fabrication.
Two techniques are known in the prior art for fabrication of ultra-thin SOI MOS transistors. The first technique requires nitride protection of a gate area and local oxidation of silicon (LOCOS) to provide a thin gate area. For ultra-thin SOI transistor fabricated by LOCOS, the thinned gate region has to be larger than the gate length by at least one alignment tolerance. The thickness of the sidewall oxide has to be larger than two alignment tolerances otherwise the silicon in this region will be completely removed during sidewall oxide etching, causing a disconnection between the source/drain regions and the channel region. However, the resistance of a thin or ultra-thin drain extension region, once formed by LOCOS, is too large for efficient use in high performance devices.
The second technique is used for conventional SOI device fabrication and requires a raised source/drain process. Such a raised source/drain process requires a seed silicon layer. Without such a seed silicon layer, selective growth of silicon cannot be accomplished. However, when the thickness of the top silicon is very thin, e.g., no thicker than 10 nm, all of the silicon in the source and drain region will be completely removed during any etching process for gate oxide sidewall formation. As a result, selective silicon growth cannot occur and the source/drain regions cannot be formed.
A transistor structure includes a main gate silicon active region having a thickness of less than or equal to 30 nm; and auxiliary gate active regions located on either side of said main gate silicon active region, said auxiliary gate active regions being spaced a distance from said main gate active region of about 200 nm. A method of forming an ultra-thin SOI MOS transistor includes preparing a silicon wafer, including forming a top silicon layer having a thickness of between about 200 nm to 100 nm, thinning the top silicon layer to a thickness of between about 10 nm to 30 nm, and forming an oxide layer over the top silicon layer; forming a layer of material taken from the group of material consisting of polysilicon and silicide; forming an oxide cap on the formed layer of material, and etching the oxide cap and layer of material to form a main gate electrode and an auxiliary gate electrode on either side thereof; forming an oxide layer over the structure and etching the oxide layer to form sidewall oxide structures about the gate electrodes; depositing a layer of material taken from the group of material consisting of polysilicon, silicide and metal, etching the newly deposited layer of material; and metallizing the structure.
An object of the invention is to provide a method of fabricating an ultra-thin SOI MOS transistor having a top silicon layer less than 20 nm thick.
Another object of the invention is to provide a SOI MOS transistor which is reliable and has a good production yield.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.